DRV8317 datasheet(7/69 Pages) TI

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7.4 Thermal Information

THERMAL METRIC(1)

DRV8317

UNIT

REE (WQFN)

RθJA

Junction-to-ambient thermal resistance (JEDEC 4-layer PCB, 6 thermal vias)

36.4

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

23.7

°C/W

RθJB

Junction-to-board thermal resistance

°C/W

ΨJT

Junction-to-top characterization parameter

0.6

°C/W

ΨJB

Junction-to-board characterization parameter

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

4.1

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLIES

IVMQ

VM sleep mode current

VVM = 12 V, nSLEEP = 0, TA = 25 °C

1.7

µA

nSLEEP = 0, TA = 125 °C

µA

IVMS

VM standby mode current

VVM = 12 V, nSLEEP = 1, INHx = INLx =

0, SPI = 'OFF', TA = 25 °C

nSLEEP = 1, INHx = INLx = 0, SPI =

'OFF'

IVM

VM operating mode current

VVM = 12 V, nSLEEP = 1, fPWM = 25 kHz,

TA = 25 °C

VVM = 12 V, nSLEEP = 1, fPWM = 200

kHz, TA = 25 °C

nSLEEP =1, fPWM = 25 kHz

nSLEEP =1, fPWM = 200 kHz

VAVDD

Analog regulator voltage

VVM ≥ 6V, VVIN_AVDD ≥ 6V, 0 mA ≤ IAVDD ≤

80 mA

3.15

3.3

3.45

VAVDD

Analog regulator voltage

4.5V ≤ VVM < 6V, 4.5V ≤ VVIN_AVDD < 6V,

0 mA ≤ IAVDD ≤ 80 mA

3.15

3.3

3.45

IAVDD

Analog regulator external load

4.5V ≤ VVM < 6V, 4.5V ≤ VVIN_AVDD < 6V

IAVDD

Analog regulator external load

VVM ≥ 6V, VVIN_AVDD ≥ 6V

IAVDD_LIM

Analog regulator current limit

VAVDD ≥ 2.7V, soft short to GND

100

125

150

CAVDD

Capacitance for AVDD

External load IAVDD = 0 mA

0.5

2.2

7.05

External load 0mA ≤ IAVDD ≤ 80 mA

2.35

4.7

7.05

VCP

Charge pump regulator voltage

4.5V ≤ VVM < 6V, CP with respect to VM

5.5

VCP

Charge pump regulator voltage

VVM ≥ 6V, CP with respect to VM

4.5

5.5

tWAKE

Wakeup time

VVM > VUVLO, nSLEEP = 1 to output

ready

tWAKE_CSA

Wakeup time for CSA

VCSAREF > VCSAREF_UV to SOx ready,

when nSLEEP = 1

µs

tSLEEP

Turn-off time

nSLEEP = 0 to driver tri-stated

100

200

µs

tRST

Reset Pulse time

nSLEEP = 0 period to reset faults

µs

FOUR-LEVEL INPUTS (GAIN, MODE, SLEW)

VL1

Input mode 1 voltage

Tied to AGND

0.2*AVD

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DRV8317

SLVSGT3 – DECEMBER 2022

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