DRV8317 datasheet(50/69 Pages) TI

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8.6.12 VMUV_WARN_THR Register (Offset = 18h) [Reset = 0000h]

VMUV_WARN_THR is shown in Figure 8-39 and described in Table 8-22.

Return to the Table 8-9.

Figure 8-39. VMUV_WARN_THR Register

PARITY

RESERVED

R/W-0h

R-0-0h

VMUV_WARN_RTH

VMUV_WARN_FTH

R/W-0h

Table 8-22. VMUV_WARN_THR Register Field Descriptions

Bit

Field

Type

Reset

Description

PARITY

R/W

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-8

RESERVED

R-0

Reserved

7-4

VMUV_WARN_RTH

R/W

VM under voltage warning rising threshold

0h = 5.62V

1h = 6.25V

2h = 6.87V

3h = 7.5V

4h = 8.12V

5h = 8.75V

6h = 9.37V

7h = 10.00V

8h = 10.62V

9h = 11.25V

Ah = 11.87V

Bh = 12.5V

Ch = 13.75V

Dh = 15.00V

Eh = 16.25V

Fh = 17.5V

3-0

VMUV_WARN_FTH

R/W

VM under voltage warning falling threshold

0h = 5.4V

1h = 6.0V

2h = 6.6V

3h = 7.2V

4h = 7.8V

5h = 8.4V

6h = 9.0V

7h = 9.6V

8h = 10.2V

9h = 10.8V

Ah = 11.4V

Bh = 12.0V

Ch = 13.2V

Dh = 14.4V

Eh = 15.6V

Fh = 16.8V

DRV8317

SLVSGT3 – DECEMBER 2022

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