DRV8317 datasheet(53/69 Pages) TI

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8.6.15 CSA_CTRL Register (Offset = 23h) [Reset = 0008h]

CSA_CTRL is shown in Figure 8-42 and described in Table 8-25.

Return to the Table 8-9.

Figure 8-42. CSA_CTRL Register

PARITY

RESERVED

R/W-0h

R-0-0h

RESERVED

CSA_EN

RESERVED

CSA_GAIN

R-0-0h

R/W-1h

R-0-0h

R/W-0h

Table 8-25. CSA_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

PARITY

R/W

Parity Bit if SPI_PEN is set to '1' otherwise reserved

14-4

RESERVED

R-0

Reserved

CSA_EN

R/W

Enable CSA

0h = CSA is disabled

1h = CSA is enabled

RESERVED

R-0

Reserved

1-0

CSA_GAIN

R/W

CSA Gain settings

0h = CSA gain is 0.25 V/A

1h = CSA gain is 0.5 V/A

2h = CSA gain is 1 V/A

3h = CSA gain is 2 V/A

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DRV8317

SLVSGT3 – DECEMBER 2022

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