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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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HCS08 Fiches technique(PDF) 186 Page - NXP Semiconductors |
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HCS08 Fiches technique(HTML) 186 Page - NXP Semiconductors |
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186 / 374 page  Multi-Purpose Clock Generator (S08MCGV1) MC9S08JM60 Series Data Sheet, Rev. 5 186 Freescale Semiconductor 12.3.3 MCG Trim Register (MCGTRM) 7 6 5 432 1 0 R TRIM W POR: 1 0 0 0 0 0 0 0 Reset: U U U UUU U U Figure 12-5. MCG Trim Register (MCGTRM) Table 12-3. MCG Trim Register Field Descriptions Field Description 7:0 TRIM MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period. An additional fine trim bit is available in MCGSC as the FTRIM bit. If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from the nonvolatile memory location to this register. |
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