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DSP56857 Fiches technique(PDF) 83 Page - Freescale Semiconductor, Inc

No de pièce DSP56857
Description  Digitial Signal Controller
PDF  662 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

DSP56857 Fiches technique(HTML) 83 Page - Freescale Semiconductor, Inc

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Power, Ground and Peripheral Signals
Overview, Rev. 4
Freescale Semiconductor
2-15
RESET
Input
Reset—This input is a direct hardware reset on the
processor. When RESET is asserted low, the
device is initialized and placed in the Reset state.
A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip
operating mode is latched from the MODA, MODB,
and MODC pins.
To ensure complete hardware reset, RESET and
TRST should be asserted together. The only
exception occurs in a debugging environment
when a hardware device reset is required and it is
necessary not to reset the JTAG/EOnCE module.
In this case, assert RESET. Do not assert TRST.
11
11
1
RSTO
Output
Reset Output—This output is asserted on any
reset condition (external reset, low voltage,
software, or COP).
11
11
1
Table 2-9. Serial Communication Interface 0
Signal Name
Signal Type
Signal Description
853
Pins
854
Pins
855
Pins
857
Pins
858
Pins
RXDO
(GPIOE0)
Input
Input / Output
Serial Receive Data 0—This input receives
byte-oriented serial data and transfers it to the
SCI0 receive shift receiver.
Port E GPIO 0—This is a General Purpose I/O pin
capable of being independently programmed as an
input or output pin.
11
11
1
TXDO
(GPIOE1)
Output(Z)
Input / Output
Serial Transmit Data 0—This signal transmits
data from the SCI0 transmit data register.
Port E GPIO 1—This is a General Purpose I/O pin
capable of being independently programmed as an
input or output pin.
11
11
1
Table 2-8. Interrupt and Program Control (Continued)
Signal Name
Signal Type
Signal Description
853
Pins
854
Pins
855
Pins
857
Pins
858
Pins



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