DSP56857 datasheet(52/662 Pages) FREESCALE

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56800E Core Description

5685X Digital Signal Controller User Manual, Rev. 4

1-20

Freescale Semiconductor

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Interrupt control logic

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A Program Counter (PC)

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Two special registers for Fast Interrupts:

— Fast Interrupt Return Address Register (FIRA)

— Fast Interrupt Status Register (FISR)

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Seven user-accessible status and control registers:

— two-level deep Hardware Stack (HWS)

— Loop Address (LA) register

— Loop Address (LA2) register 2

— Loop Count (LC) register

— Loop Count (LC2) register 2

— Status Register (SR)

— Operating Mode Register (OMR)

The Operating Mode Register (OMR) is a programmable register to control the operation of the

56800E core, including the memory-map configuration. The initial operating mode is typically

latched on reset from an external source; it can subsequently be altered under program control.

The Loop Address (LA) and Loop Count (LC) registers work in conjunction with the hardware

stack to support no-overhead hardware looping. The Hardware Stack is an internal

Last-In-First-Out (LIFO) buffer consisting of two, 24-bit words and stores the address of the first

instruction of a hardware DO loop. When executing the DO instruction begins a new Hardware

Loop, the address of the first instruction in the Loop is pushed onto the Hardware Stack. When a

Loop finishes normally or an ENDDO instruction is encountered, the value is popped from the

Hardware Stack. This process allows one Hardware DO Loop to be nested inside another.

1.4.10 Bit Manipulation Unit

The bit-manipulation unit performs bit field operations on data memory words, peripheral

registers, and registers within the 56800E core. It is capable of testing, setting, clearing, or

inverting individual or multiple bits within a 16-bit word. The bit-manipulation unit can also test

bytes for branch-on-bit field instructions.

DSP56857 Fiches technique(PDF) 52 Page - Freescale Semiconductor, Inc