DSP56857 datasheet(48/662 Pages) FREESCALE

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56800E Core Description

5685X Digital Signal Controller User Manual, Rev. 4

1-16

Freescale Semiconductor

Figure 1-7. 56800E Core Block Diagram

Instruction execution is pipelined to take advantage of the parallel units, significantly decreasing

the execution time for each instruction. For example, all within a single execution cycle, it is

possible for the data ALU to perform a multiplication operation, for the AGU to generate up to

two addresses, and for the program controller to prefetch the next instruction.

The major components of the 56800E core include the following:

•

Address buses

•

Data buses

•

Data Arithmetic Logic Unit (ALU)

Data

56800E Core

Arithmetic

Logic Unit

(ALU)

XAB2

PAB

PDB

CDBW

CDBR

XDB2

Program

Memory

Data

Memory

IPBus

Interface

External

Bus

Interface

Bit-

Manipulation

Unit

M01

Address

XAB1

Generation

Unit

(AGU)

LA2

HWS0

HWS1

FIRA

OMR

FISR

LC2

Instruction

Decoder

Interrupt

Unit

Looping

Unit

Program Control Unit

ALU1

ALU2

MAC and ALU

EOnCE™

JTAG™

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