DSP56857 datasheet(323/662 Pages) FREESCALE

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ESSI Configurations

Enhanced Synchronous Serial Interface (ESSI), Rev. 4

Freescale Semiconductor

12-23

12.6 ESSI Configurations

Figure 12-9 and Figure 12-10 illustrate the main ESSI configurations. These pins support all

transmit and receive functions shown. Section 12.5 describes the clock, frame sync, and data

timing relationships in each of the modes available. Some modes do not require the use of all six

pins. In this case, these pins can be used as MPIO pins, if desired.

Note:

The MPIO is a separate module alternatively controlling the function and state of the

I/O pins. See the MPIO module definition for alternate functions of the I/O pins

defined here.

Figure 12-9. Asynchronous (SYN=0) ESSI Configurations

STD

SRD

SCK

SC2

SC0

SC1

ESSI+GPIO

ESSI Internal Asynchronous Clock (SCD0=1,SCKD=1,SCD1=1,SCD2=1,SYN=0)

STD

SRD

SCK

SC2

SC0

SC1

ESSI+GPIO

ESSI External Asynchronous Clock (SCD0=0,SCKD=0,SCD1=0,SCD2=0,SYN=0)

STD

SRD

SCK

SC2

SC0

SC1

ESSI+GPIO

ESSI Asynchronous Clock (SCD0=1, SCKD=0, SCD1=1,SCD2=0, SYN=0)

STD

SRD

SCK

SC2

SC0

SC1

ESSI+GPIO

ESSI Asynchronous Clock (SCD0=0, SCKD=1, SCD1=0, SCD2=1, SYN=0)

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