CS43L36 datasheet(21/89 Pages) CIRRUS

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DS1081F3

CS43L36

4.1 Digital Volume Control

• Class H amplifier. The HP output amplifiers, described in Section 4.3, use a patented Cirrus Logic four-mode

Class H technology that maintains high performance and maximizes operating efficiency of a typical Class AB

amplifier.

• Clocking architecture. Described in Section 4.4, the clock for the device can be supplied internally from an

integrated fractional-N PLL using ASP_SCLK/ as the source clock or the internal PLL can be bypassed and derived

directly from the input pin.

• Serial port. The CS43L36 TDM/I2S (ASP) port is a highly configurable serial port. See Section 4.5.

The ASP can operate in TDM Mode, which includes full-duplex communication, flexible data structuring via control

port registers, clock slave mode, and higher bandwidth, enabling more data to be transferred to and from the device.

• Sample-rate converters (SRCs). SRCs, described in Section 4.6, are used to bridge different sample rates at the

serial ports within the digital-processing core. SRCs can be bypassed.

• Headset interface. This interface is described in Section 4.7.

• Power management. Several control registers provide independent power-down control of the analog and digital

sections of the CS43L36, allowing operation in select applications with minimal power consumption. Power

management considerations are described in Section 4.9.

• Control-port operation. The control port, described in Section 4.10, provides access to the registers for configuring

the DAC. The control port operation may be completely asynchronous with respect to the audio sample rates. To

avoid potential interference problems, control-port data pins must remain static if no operation is required.

• Resets. Section 4.11 describes the reset options—power-on reset (POR), asserting and RESET.

• Interrupts. The CS43L36 includes an open-drain interrupt output, INT. Interrupt mask registers control whether an

event associated with an interrupt status/mask bit pair triggers the assertion of INT. See Section 4.12.

4.1 Digital Volume Control

The internal stereo volume control is shown in Fig. 4-2. Each input can be attenuated via CHx_VOLy. Outputs are

available as a source for the DACs.

4.1.1

Attenuation Values

The volume control contains programmable attenuation blocks that are configured as described in the CHx_VOLy field

descriptions in Section 7.11.1—Section 7.11.2. For all settings except 0 dB, attenuation on the mixer input includes an

offset that increases as attenuation increases, as follows:

• For commonly used –6n dB (n

1, 2, etc.}) attenuation settings, the offset rounds the attenuation exactly to the

desired 1/2n factor (e.g., 20Log(1/2) = 6.021 dB, not 6.000 dB).

• For attenuation settings other than –6n dB, the always positive offset provides slightly more attenuation, giving

enough margin to avoid mixer clipping.

Figure 4-2. Digital Volume Control Subblocks

Volume Control

Output A

Output B

Serial Port A/SRC

Serial Port B/SRC

Attenuation

CHA_VOL on p. 76

CHB_VOL on p. 77

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