CS43L36 datasheet(40/89 Pages) CIRRUS

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DS1081F3

CS43L36

4.6 Sample-Rate Converters (SRCs)

4.5.7

Recommended Serial-Port Power-Up and Power-Down Strategies

Although multiple safeguards and controls are implemented to prevent a run on the FIFOs involved in passing data from

the input port to the output port, the following power-up sequence is recommended. Section 5 gives detailed sequences.

1. Configure all playback channel characteristics—bit resolution, channel select, source (DAI), native/isochronous,

sample rates, etc.

2. Power up playback, and ASRCs.

3. Release the PDN_ALL bit.

4. Power up the serial ports (DAI).

The following power-down sequence is recommended:

1. Power down the playback path.

2. Power down the serial ports.

4.6 Sample-Rate Converters (SRCs)

SRCs bridge different sample rates at the serial ports within the digital-processing core. SRCs are used for the following:

• Two ASP input channels (Channels 1 and 2).

• SRCs are bypassable by setting SRC_BYPASS_DAC (see p. 60).

An SRC’s digital-processing side (as opposed to its serial-port side) connects to the DAC. Multirate DSP techniques are

used to up-sample incoming data to a very high rate and then down-sample to the outgoing rate. Internal filtering is

designed so that a full-input audio bandwidth of 20 kHz is preserved if the input and output sample rates are at least

44.1 kHz. If the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid

aliasing artifacts in the output signal.

The following restrictions must be met:

•The Fso-to-FSI ratio must be no more than 1:6 or 6:1. For example, if the DAC is at 48 kHz, the input to the SRC

must be at least 8 kHz.

• SRC operation cannot be changed on-the-fly. Before changing the SRC operation (e.g., changing SRC frequencies

or bypassing or adding the SRCs), the user must follow the power sequences provided in Section 4.5.7.

• The MCLK frequency must be as close as possible to, but not less than the minimum SRC MCLK frequency,

MCLKMIN, which must be at least 125 times the higher of the two sample rates (FSI or Fso).

For example, if Fso is 48 kHz and FSI is 32 kHz, the MCLK must be as close as possible to, but not less than, an

MCLKMIN of 6.0 MHz. The MCLK frequency for the SRCs is configured through CLK_IASRC_SEL (see p. 66).

Table 4-10 shows settings for the supported sample rates and corresponding MCLKINT frequencies.

Jitter in the incoming signal has little effect on rate-converter dynamic performance. It does not affect the output clock.

A digital PLL continually measures the heavily low-pass-filtered phase difference and the frequency ratio between input

and output sample rate clocks. It uses the data to dynamically adjust coefficients of a linear time-varying filter that

processes a synchronously oversampled version of the input data. The filter output is resampled to the output sample rate.

For input serial ports, input and output sample-rate clocks are respectively derived from the external serial-port sample

clock (x_LRCK) and the internal Fs clock. FS_EN (see p. 66) must be set according to the FSI or Fso SRC sample rates.

Table 4-10. Supported Sample Rates and Corresponding MCLKINT Encodings

Fsint

(kHz)

Serial Port Sample Rate (kHz)

8.0

11.025

11.029

12 16

22.05

22.059

24 32 44.1

44.118

48 88.2

88.235

176.4

176.471

192

44.1

00 00

Note: SRC MCLKINT Freq= 00 (6 MHz), 01 (12 MHz), 11 (24 MHz), configured in CLK_IASRC_SEL (see p. 66)

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