CS43L36 datasheet(74/89 Pages) CIRRUS

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DS1081F3

CS43L36

7.7 Headset Interface Registers

WAKEB_

CLEAR

WAKE output clear. Applicable only if WAKEB_MODE = 0 and an event triggers the WAKE output to latch low.

0 (Default) WAKE output normal operation. If WAKEB_MODE = 1, WAKEB_CLEAR does not deassert WAKE, but clears

TIP_SENSE_PLUG, TIP_SENSE_UNPLUG in the VP domain.

1WAKE output deasserted (the TIP_SENSE_PLUG, TIP_SENSE_UNPLUG bits in the VP domain are also cleared).

1.This bit can be changed only if LATCH_TO_VP is enabled (see p. 74).

7.7.2

Tip Sense Control 2

Address 0x1B73

R/W

432

TIP_SENSE_CTRL

TIP_SENSE_INV

—

TIP_SENSE_DEBOUNCE

Default

010

Bits

Name

Description

7:6

TIP_SENSE_

CTRL

Tip sense control.Configures operation of the tip-sense circuit.

Note: This bit can be updated only if LATCH_TO_VP (see p. 74) is enabled.

00 (Default) Disabled. The tip-sense circuit is powered down and does not report to the status registers (TIP_

SENSE_PLUG and TIP_SENSE_UNPLUG in the VP domain are also cleared).

01 Digital input. Internal weak current source pull-up is disabled.

10 Reserved

11 Short detect. Internal weak current source pull-up is enabled.

5TIP_SENSE_

INV

Tip sense invert. Used to invert the signal from the tip-sense circuit. Updatable only if LATCH_TO_VP is enabled.

0 (Default) Not inverted

1Inverted

4:2

—

Reserved

1:0

TIP_SENSE_

DEBOUNCE

Tip sense debounce time. Sets tip sense unplug event (TIP_SENSE = 0) debounce time before status is reported.

Timings are approximate and vary with MCLKINT and FsINT.

00 No debounce

01 200 ms

10 (Default) 500 ms

11 1000 ms

7.7.3

Mic Detect Control 1

Address 0x1B75

R/W

5432

LATCH_TO_VP EVENT_STATUS_SEL

—

Default

011

111

Bits

Name

Description

7LATCH_

TO_VP

Latch to VP registers. Controls the transfer of writable control registers in the VD_FILT supply domain to duplicate registers

in the VP supply domain. Can be used to enable setting sticky status bits in the VP domain.

0 (Default) Inhibits the transfer of VD_FILT registers to VP registers (latched mode). Enables the setting of VP sticky

status latches.

1 Transfers VD_FILT fields to VP fields (transparent mode). Disables setting of VP sticky status latches.

Affected registers:

• TIP_SENSE_CTRL on p. 74

• TIP_SENSE_INV on p. 74

• M_HP_WAKE on p. 73

• WAKEB_MODE p. 73

Note: The description of PDN_ALL on p. 62 describes the interdependency between LATCH_TO_VP and PDN_ALL.

6EVENT_

STATUS_

SEL

Event status selection. Selects the level of processing on readable status originating in the VP supply domain.

0 (Default) Raw (unprocessed) status events are selected.

1 Sticky processed status events are selected.

Affected registers:

• TIP_SENSE_PLUG on p. 68

• TIP_SENSE_UNPLUG on p. 68

•

5:0

—

Reserved

Bits

Name

Description

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