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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD6676EBZ Fiches technique(PDF) 88 Page - Analog Devices |
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AD6676EBZ Fiches technique(HTML) 88 Page - Analog Devices |
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88 / 90 page  AD6676 Data Sheet Rev. D | Page 88 of 90 CLKSYN Reference Divider and SYSREF Control Register Address: 0x2BB, Reset: 0xB9, Name: CLKSYN_R_DIV Table 130. Bit Descriptions for CLKSYN_R_DIV Bits Bit Name Description Reset Access [7:6] R_DIV 00 = div-by-1; 01 = div-by-2; 10 = div-by-4; 11 = multiply-by-2. 10 RW [5:4] RESERVED 0x3 RW 3 SYSREF_CTRL SYSREF Input Sampling Clock. 1 RW 0 = use clock synthesizer reference clock. 1 = use internal clock at FADC/2 (use for nonclock synthesizer case). 2 CLKIN_IMPED CLKIN Impedance. 0 RW 0 = configure CLK± as 100 Ω termination, configuration for clock synthesizer disabled. 1 = configure CLK+ as high-Z, configuration for clock synthesizer enabled. [1:0] RESERVED 0x1 RW CLKSYN Status Register Address: 0x2BC, Reset: 0x80, Name: CLKSYN_STATUS Table 131. Bit Descriptions for CLKSYN_STATUS Bits Bit Name Description Reset Access [7:4] RESERVED 0x8 R 3 PLL_LCK Clock Synthesizer Lock Bit (1 = lock). 0x0 R 2 RESERVED 0x0 R 1 VCO CAL BUSY VCO Calibration Busy (0 = done). 0x0 R 0 CP CAL DONE Charge Pump Calibration Done (1 = done). 0x0 R JESDSYN Status Register Address: 0x2DC, Reset: 0x80, Name: JESDSYN_STATUS Table 132. Bit Descriptions for JESDSYN_STATUS Bits Bit Name Description Reset Access [7:4] RESERVED 0x8 R 3 PLL_LCK JESD204 PLL Synthesizer Lock Bit (1 = lock). 0x0 R 2 RESERVED 0x0 R 1 VCO CAL BUSY VCO Calibration Busy (0 = done). 0x0 R 0 CP CAL DONE Charge Pump Calibration Done (1 = done). 0x0 R Shuffler Control Register Address: 0x340, Reset: 0x03, Name: SHUFFLE_CTRL Table 133. Bit Descriptions for SHUFFLE_CTRL Bits Bit Name Description Reset Access [7:2] RESERVED 0x00 RW 1 RESERVED 1 RW 0 EN_ADAPTIVE_SHUFFLE Enable Adaptive Flash Shuffling. 1 RW |
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