AD6676EBZ datasheet(80/90 Pages) AD

80 / 90 page

AD6676

Data Sheet

Rev. D | Page 80 of 90

Bits

Bit Name

Settings

Description

Reset

Access

Scrambling enabled.

[6:5]

RESERVED

0x0

[4:0]

L Parameter.

0x00

00000

One lane.

00001

Two lanes.

JESD204 F Register

Address: 0x1C4, Reset: 0x03, Name: F

Table 95. Bit Descriptions for F

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

Octest per Frame per Lane.

0x03

00000001

F = 2

00000011

F = 4

JESD204 K Register

Address: 0x1C5, Reset: 0x1F, Name: K

Table 96. Bit Descriptions for K

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

0x0

[4:0]

Frames per multiframe. Number of frames per multiframe is the register

value plus one.

0x1F

JESD204 M Register

Address: 0x1C6, Reset: 0x01, Name: M

Table 97. Bit Descriptions for M

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

0x01

00000001

Two converters (I/Q data).

JESD204 S Register

Address: 0x1C9, Reset: 0x00, Name: S

Table 98. Bit Descriptions for S

Bits

Bit Name

Settings

Description

Reset

Access

[7:5]

RESERVED

0x0

[4:0]

0x00

00000

One sample per frame (the only valid option).

JESD204 RES1 Register

Address: 0x1CB, Reset: 0x00, Name: RES1

Table 99. Bit Descriptions for RES1

Bits

Bit Name

Description

Reset

Access

[7:0]

RES1

0x00

AD6676EBZ Fiches technique(PDF) 80 Page - Analog Devices

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