AD6676EBZ datasheet(46/90 Pages) AD

46 / 90 page

AD6676

Data Sheet

Rev. D | Page 46 of 90

Figure 118 shows a simplified block diagram of the AD6676

JESD204B link mapping the 16-bit I and Q outputs onto the two

separate lanes. Other configurations are also possible, such as

combining the I and Q outputs onto a single lane (fDATA_IQ ≤

153.6 MSPS) or changing the mapping of the I and Q output

paths. In any case, the 16-bit I and Q data are each broken into

two octets (eight bits of data). Bit 15 (MSB) through Bit 8 are in

the first octet. The second octet contains Bit 7 through Bit 0

(LSB). The four resulting octets (2 I octets and 2 Q octets) may

be scrambled. Scrambling is optional but is available to avoid

spectral peaks when transmitting similar digital data patterns.

The scrambler uses a self synchronizing polynomial-based

algorithm defined by the equation 1 + x14 + x15. The descrambler

in the receiver must be a self synchronizing version of the

scrambler polynomial.

The four octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder takes eight bits of data (an octet) and encodes

them into a 10-bit symbol. Figure 119 shows how the 16-bit I or

Q data is taken from the final decimation stage, formed into

octets, the two octets are scrambled, and how the octets are

encoded into two 10-bit symbols.

ADC

SYSREF±

SYNCINB±

CONVERTER 0

CONVERTER 1

SERDOUT0–,

SERDOUT0+

SERDOUT1–,

SERDOUT1+

LANE SWAP

(SPI REG 0x1E1)

JESD204B LINK

CONTROL

(L.M.F.M.S)

(SPI REG 0x1C3

TO 0x1C9)

FRAMER

SWAP

(SPI

REG 0x1E1)

Figure 118. Transmit Link Simplified Block Diagram

8-BIT/10-BIT

ENCODER

(0x1E4)

SERDOUT0±

SERDOUT1±

SERIALIZER

ADC

SYMBOL0

SYMBOL1

ADC TEST PATTERNS

(REG 0x1E5)

JESD204B SAMPLE

CONSTRUCTION

JESD204B TEST

PATTERNS

(0x1E5)

FRAME

CONSTRUCTION

JESD204B TEST

PATTERNS

(REG 0x1E5,

REG 0x1F8

TO REG 0x1FF)

JESD204B TEST

PATTERNS

(REG 0x1E5,

REG 0x1F8 TO

REG 0x1FF)

SCRAMBLER

1 + x14 + x15

(OPTIONAL

VIA 0x1C3)

a b c d e f g h i j

a b

i j a b

i j

16-BIT

Figure 119. Digital Formatting of JESD204B Lanes

TRANSPORT

LAYER

PHYSICAL

LAYER

DATA LINK

LAYER

OUTPUT

SAMPLE

CONSTRUCTION

FRAME

CONSTRUCTION

SCRAMBLER

ALIGNMENT

CHARACTER

GENERATION

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SERIALIZER

PROCESSED

SAMPLES

FROM ADC

SYSREF±

SYNCINB±

Figure 120. Data Flow

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