AD6676EBZ datasheet(60/90 Pages) AD

60 / 90 page

AD6676

Data Sheet

Rev. D | Page 60 of 90

Figure 143 and Figure 144 show the measured sideband level in

dBc that results if a 1 mV p-p continuous wave tone has frequencies

common among switching regulators are injected onto the 1.1 V

and 2.5 V analog supplies. Note that the sideband level increases

at roughly 6 dB per octave in IF frequency for the 1.1 V supply

domain case because the supply noise results in PM modulation

that affects the clock jitter.

–74

–76

–78

–80

–82

–84

–86

–88

–90

100

200

400

500

300

150

350

450

250

IF INPUT FREQUENCY (MHz)

400MHz

800MHz

1600MHz

3200MHz

Figure 143. Sideband Spur Level for 1 mV p-p, Continuous Wave Tone

Injected on Analog 1.1 V Supply Domain

–94

–96

–98

–100

–102

–104

–106

–108

–110

100

200

400

500

300

150

350

450

250

IF INPUT FREQUENCY (MHz)

400MHz

800MHz

1600MHz

3200MHz

Figure 144. Sideband Spur Level for 1 mV p-p, Continuous Wave Tone

Injected on Analog 2.5 V Supply Domain

On the digital 1.1 V supply, amplitude modulation on the

JESD204B high speed serializer supply (VDDHSI) can

negatively impact the eye opening of the digital data output

stream. For these reasons, low noise LDOs, such as the

ADP1752, that have a worst-case accuracy of 2% over line, load,

and temperature are used for the analog VDD2 and VDD1

supplies. The same regulator is used for the digital VDDD for

its low dropout characteristics, power supply rejection ratio, and

load capability. Although the digital VDDD is used for the less

critical VDDIO supply, a smaller, lower cost regulator such as

the ADP121, can also be used to supply 1.8 V.

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