ACEX1 datasheet(1/86 Pages) ETC

No de pièce	ACEX1

Description	Programmable Logic Device Family

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Altera Corporation

1

ACEX 1K

Programmable Logic Device Family

September 2001, ver. 3.3

Data Sheet

A-DS-ACEX-3.3

13

Features...

s

Programmable logic devices (PLDs), providing low cost

system-on-a-programmable-chip (SOPC) integration in a single

device

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

–

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

–

Logic array for general logic functions

s

High density

–

10,000 to 100,000 typical gates (see Table 1)

–

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be

used without reducing logic capacity)

s

Cost-efficient programmable architecture for high-volume

applications

–

Cost-optimized process

–

Low cost solution for high-performance communications

applications

s

System-level features

–

MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

–

Bidirectional I/O performance (setup time [tSU] and clock-to-

output delay [tCO]) up to 250 MHz

–

Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2

for 3.3-V operation at 33 MHz or 66 MHz

Table 1. ACEXTM 1K Device Features

Feature

EP1K10

EP1K30

EP1K50

EP1K100

Typical gates

10,000

30,000

50,000

100,000

Maximum system gates

56,000

119,000

199,000

257,000

Logic elements (LEs)

576

1,728

2,880

4,992

EABs

3

6

10

12

Total RAM bits

12,288

24,576

40,960

49,152

Maximum user I/O pins

136

171

249

333

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ACEX1 Fiches technique(PDF) 1 Page - List of Unclassifed Manufacturers

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