ACEX1 datasheet(23/86 Pages) ETC

23 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Clearable Counter Mode

The clearable counter mode is similar to the up/down counter mode, but

it supports a synchronous clear instead of the up/down control. The clear

function is substituted for the cascade-in signal in the up/down counter

mode. Two 3-input LUTs are used; one generates the counter data, and

the other generates the fast carry bit. Synchronous loading is provided by

a 2-to-1 multiplexer. The output of this multiplexer is ANDed with a

synchronous clear signal.

Internal Tri-State Emulation

Internal tri-state emulation provides internal tri-states without the

limitations of a physical tri-state bus. In a physical tri-state bus, the

tri-state buffers’ output enable (OE) signals select which signal drives the

bus. However, if multiple OE signals are active, contending signals can be

driven onto the bus. Conversely, if no OE signals are active, the bus will

float. Internal tri-state emulation resolves contending tri-state buffers to a

low value and floating buses to a high value, thereby eliminating these

problems. The Altera software automatically implements tri-state bus

functionality with a multiplexer.

Clear & Preset Logic Control

Logic for the programmable register’s clear and preset functions is

controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The

clear and preset control structure of the LE asynchronously loads signals

into a register. Either LABCTRL1 or LABCTRL2 can control the

asynchronous clear. Alternatively, the register can be set up so that

LABCTRL1

implements an asynchronous load. The data to be loaded is

driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the

During compilation, the compiler automatically selects the best control

signal implementation. Because the clear and preset functions are active-

low, the Compiler automatically assigns a logic high to an unused clear or

preset.

The clear and preset logic is implemented in one of the following six

modes chosen during design entry:

Asynchronous clear

Asynchronous preset

Asynchronous clear and preset

Asynchronous load with clear

Asynchronous load with preset

Asynchronous load without clear or preset

ACEX1 Fiches technique(PDF) 23 Page - List of Unclassifed Manufacturers