ACEX1 datasheet(56/86 Pages) ETC

56 / 86 page

Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Table 24. EAB Timing Microparameters

Note (1)

Symbol

Parameter

Conditions

tEABDATA1

Data or address delay to EAB for combinatorial input

tEABDATA2

Data or address delay to EAB for registered input

tEABWE1

Write enable delay to EAB for combinatorial input

tEABWE2

Write enable delay to EAB for registered input

tEABRE1

Read enable delay to EAB for combinatorial input

tEABRE2

Read enable delay to EAB for registered input

tEABCLK

EAB register clock delay

tEABCO

EAB register clock-to-output delay

tEABBYPASS

Bypass register delay

tEABSU

EAB register setup time before clock

tEABH

EAB register hold time after clock

tEABCLR

EAB register asynchronous clear time to output delay

tAA

Address access delay (including the read enable to output delay)

tWP

Write pulse width

tRP

Read pulse width

tWDSU

Data setup time before falling edge of write pulse

(5)

tWDH

Data hold time after falling edge of write pulse

(5)

tWASU

Address setup time before rising edge of write pulse

(5)

tWAH

Address hold time after falling edge of write pulse

(5)

tRASU

Address setup time before rising edge of read pulse

tRAH

Address hold time after falling edge of read pulse

tWO

Write enable to data output valid delay

tDD

Data-in to data-out valid delay

tEABOUT

Data-out delay

tEABCH

Clock high time

tEABCL

Clock low time

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