ACEX1 datasheet(3/86 Pages) ETC

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Altera Corporation

ACEX 1K Programmable Logic Device Family Data Sheet

Software design support and automatic place-and-route provided by

Altera development systems for Windows-based PCs and Sun

SPARCstation, and HP 9000 Series 700/800 workstations

Flexible package options are available in 100 to 484 pins, including

the innovative FineLine BGATM packages (see Tables 2 and 3)

Additional design entry and simulation support provided by EDIF

2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

DesignWare components, Verilog HDL, VHDL, and other interfaces

to popular EDA tools from manufacturers such as Cadence,

Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,

VeriBest, and Viewlogic

Notes:

(1)

ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine

BGA packages.

(2)

Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When

planning device migration, use the I/O pins that are common to all devices.

(3)

This option is supported with a 256-pin FineLine BGA package. By using SameFrameTM pin migration, all FineLine

BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine

BGA packages.

Table 2. ACEX 1K Package Options & I/O Pin Count

Notes (1), (2)

Device

100-Pin TQFP

144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

484-Pin

FineLine BGA

EP1K10

120

136

136 (3)

EP1K30

102

147

171

171 (3)

EP1K50

102

147

186

249

EP1K100

147

186

333

Table 3. ACEX 1K Package Sizes

Device

100-Pin TQFP

144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

484-Pin

FineLine BGA

Pitch (mm)

0.50

1.0

Area (mm2)

256

484

936

289

529

Length

× width

(mm

× mm)

× 16

× 22

30.6

× 30.6

× 17

× 23

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