SPC564A80L7 datasheet(18/157 Pages) STMICROELECTRONICS

18 / 157 page

Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

18/157

Doc ID 15399 Rev 9

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Four-entry 256-bit wide line read buffer

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Prefetch controller

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Hardware and software configurable read and write access protections on a per-master

basis

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Interface to the flash array controller pipelined with a depth of one, allowing overlapped

accesses to proceed in parallel for interleaved or pipelined flash array designs

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Configurable access timing usable in a wide range of system frequencies

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Multiple-mapping support and mapping-based block access timing (0-31 additional

cycles) usable for emulation of other memory types

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Software programmable block program/erase restriction control

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Erase of selected block(s)

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Read page size of 128 bits (four words)

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ECC with single-bit correction, double-bit detection

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Program page size of 128 bits (four words) to accelerate programming

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ECC single-bit error corrections are visible to software

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Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte

address, due to ECC

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Embedded hardware program and erase algorithm

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Erase suspend, program suspend and erase-suspended program

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Shadow information stored in non-volatile shadow block

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Independent program/erase of the shadow block

1.5.9

BAM

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by

ST and is identical for all SPC564A80 MCUs. The BAM program is executed every time the

MCU is powered-on or reset in normal mode. The BAM supports different modes of booting.

They are:

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Booting from internal flash memory

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Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and

then executed)

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Booting from external memory on external bus

The BAM also reads the reset configuration half word (RCHW) from internal flash memory

and configures the SPC564A80 hardware accordingly. The BAM provides the following

features:

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Sets up MMU to cover all resources and mapping of all physical addresses to logical

addresses with minimum address translation

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Sets up MMU to allow user boot code to execute as either Power Architecture

embedded category (default) or as VLE code

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Location and detection of user boot code

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Automatic switch to serial boot mode if internal flash is blank or invalid

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Supports user programmable 64-bit password protection for serial boot mode

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Supports serial bootloading via FlexCAN bus and eSCI using standard protocol

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Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

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Supports serial bootloading of either Power Architecture code (default) or VLE code

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