PC87366 datasheet(70/240 Pages) NSC

70 / 240 page

2.0 Device Architecture and Configuration (Continued)

www.national.com

2.15.5

GPIO Pin Configuration Register

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO

Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hard-

ware to 44h, except for ports 2 and 3, that are reset to 04h.

Location:

Index F1h

Type:

R/W

Ports: 0 and 1 (with event detection capability)

Ports 2 and 3 (without event detection capability)

Bit

76543210

Name

Reserved

Event

Debounce

Enable

Event

Polarity

Event Type

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

01000100

Bit

76543210

Name

Reserved

Lock

Pull-Up

Control

Output

Type

Output

Enable

Reset

00000100

Bit

Description

Reserved

Event Debounce Enable. (Ports 0 and 1 with event detection capability). Enables transferring the signal only

after a predetermined debouncing period of time.

0: Disabled

1: Enabled (default)

Reserved. (Ports 2 and 3). Always 0.

Event Polarity. (Ports 0 and 1 with event detection capability). This bit deﬁnes the polarity of the signal that

issues an interrupt from the corresponding GPIO pin (falling/low or rising/high).

0: Falling edge or low level input (default)

1: Rising edge or high level input

Reserved. (Ports 2 and 3). Always 0.

Event Type. (Ports 0 and 1 with event detection capability). This bit deﬁnes the type of the signal that issues an

interrupt from the corresponding GPIO pin (edge or level).

0: Edge input (default)

1: Level input

Reserved. (Ports 2 and 3). Always 0.

Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to

0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O

Conﬁguration 3 register, SIOCF3).

0: No effect (default)

1: Direction, output type, pull-up and output value locked

Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.

It supports open-drain output signals with internal pull-ups and TTL input signals

0: Disabled

1: Enabled (default)

Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.

0: Open-drain (default)

1: Push-pull

Output Enable. This bit indicates the GPIO pin output state. It has no effect on the input path.

0: TRI-STATE (default)

1: Output enabled

PC87366 Fiches technique(PDF) 70 Page - National Semiconductor (TI)

PC87366 Fiches technique(HTML) 70 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL