PC87366 datasheet(67/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

2.15.1

General Description

The GPIO functional block includes 29 pins, arranged in three 8-bit ports (ports 0, 1 and 2) and one 5-bit port (port 3). All

pins in port 0 are I/O, and have full event detection capability, enabling them to trigger the assertion of IRQ, SMI and

PWUREQ signals. With the exception of bit 5 which is output only, port 1 pins are also I/O with full event detection capability.

Pins in ports 2 and 3 are I/O, but none of them has event detection capability. The sixteen runtime registers associated with

the five ports are arranged in the GPIO address space as shown in Table 27. The GPIO base address is 16-byte aligned.

Address bits 3-0 are used to indicate the register offset.

Table 27. Runtime Registers in GPIO Address Space

2.15.2

Implementation

The standard GPIO port with event detection capability (such as ports 0, 1 and 4) has four runtime registers. Each pin is

associated with a GPIO Pin Configuration register that includes seven configuration bits. Ports 2 and 3 are non-standard

ports that do not support event detection, and therefore differ from the generic model as follows:

They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers

GPEVEN2/3 and GPEVST2/3 are not available.

Only bits 3-0 are implemented in the GPIO Pin Conﬁguration registers of ports 2 and 3. Bits 6-4, associated with the

event detection functionality, are reserved.

Offset

Mnemonic

Port

Type

00h

GPDO0

GPIO Data Out 0

R/W

01h

GPDI0

GPIO Data In 0

02h

GPEVEN0 GPIO Event Enable 0

R/W

03h

GPEVST0 GPIO Event Status 0

R/W1C

04h

GPDO1

GPIO Data Out 1

R/W

05h

GPDI1

GPIO Data In 1

06h

GPEVEN1 GPIO Event Enable 1

R/W

07h

GPEVST1 GPIO Event Status 1

R/W1C

08h

GPDO2

Data Out 2

R/W

09h

GPDI2

Data In 2

0Ah

GPDO3

Data Out 3

R/W

0Bh

GPDI3

Data In 3

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