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PC87366 Fiches technique(PDF) 63 Page - National Semiconductor (TI) |
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PC87366 Fiches technique(HTML) 63 Page - National Semiconductor (TI) |
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63 / 240 page ![]() 2.0 Device Architecture and Configuration (Continued) 63 www.national.com 2.13 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION 2.13.1 Logical Device 4 (SWC) Configuration Table 24 lists the configuration registers which affect the SWC. See Sections 2.2.3 and 2.2.4 for a detailed description of these registers. Table 24. System Wake-Up Control (SWC) Configuration Registers Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible. Note 1. Note 1. The logical device registers are maintained, and all wake-up detection mechanisms are func- tional. R/W 00h 60h Base Address MSB register R/W 00h 61h Base Address LSB register. Bits 4-0 (for A4-0) are read only, 00000b. R/W 00h 70h Interrupt Number R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment RO 04h 75h Report no DMA assignment RO 04h |
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