ADMCF341_15 datasheet(19/36 Pages) AD

19 / 36 page

REV. A

ADMC(F)341

–19–

100

TUNED ICONST

DEFAULT ICONST

Figure 14. Timing Capacitor Selection

Analog Front End

The main analog inputs of the ADMC(F)341 (ISENSE1 to

ISENSE3) are connected to the ADC converter through three

front end blocks. Figure 15 shows the block diagram of a single

analog front end.

SHA TIMER

SHA

STATE

MACHINE

OVERCURRENT

COMPARATOR

SHA TIMER

COUNTER

VOLTAGE (THIS IS NOT AVAILABLE EXTERNALLY ON THE ADMC(F)341)

CURRENT

PWMSYNC

CLOCKOUT

MODECTRL REGISTER

CHANNEL SELECTION (ISENSE/V)

ADC CONVERSION

STATUS BIT

(ADC REGISTER)

SHA

–2.5

VxL

(TO ADC)

TRIP

(TO

PWMTRIP FILTER)

TRIP REF HIGH

TRIP REF LOW

Figure 15. Analog Front End Block Diagram

N–1

N+1

N+2

N+3

N+4

N+5

CYCLE

PWMSYNC

SHA TIMER

COUNTER

SHA STATUS

ISENSE INPUT

ADC REGISTER

DATA READY

SAMPLED ON

CYCLE N–2

INVALID

LSB = 1

DATA READY

SAMPLED ON

CYCLE N

INVALID

LSB = 1

DATA READY

SAMPLED ON

CYCLE N+2

DATA READY

SAMPLED ON

CYCLE N+4

TSAMPLE

TRACK

Figure 16. ADC Conversion Sequence of a Current Input

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