ADMCF341_15 datasheet(17/36 Pages) AD

17 / 36 page

REV. A

ADMC(F)341

–17–

ADC Overview

The ADC of the ADMC(F)341 is based upon the single slope

conversion technique. This approach offers an inherently mono-

tonic conversion process within the noise and stability of its

components, and there will be no missing codes.

The single slope technique has been adopted on the

ADMC(F)341 for four channels that are simultaneously con-

verted. Refer to Figure 11 for the functional schematic of the

ADC. The main inputs (ISENSE1 to ISENSE3) are connected to the

ADC converter through three front end blocks. Figure 15 shows

the block diagram of a single front end block. Each front end

block has a bipolar current amplifier (Gain = –2.5) designed to

acquire the voltage on a current-sensing resistor whose voltage

can be either positive or negative with respect to the power

supply ground rail.

The fourth channel has been configured with a serially con-

nected 4-to-1 multiplexer. Table VI shows the multiplexer input

selection codes. One of these auxiliary multiplexed channels is

used to acquire the internal voltage reference (VREF) for calibra-

tion purposes.

Table VI. ADC Auxiliary Channel Selection

MODECTRL (1)

MODECTRL (0)

Select

ADCMUX1

ADCMUX0

VAUX0

VAUX1

VAUX2

Calibration (VREF)1

ADC1

ADC2

ADC3

ADCAUX

COMP

ISENSE1

ISENSE2

ISENSE3

VAUX0

VAUX1

VAUX2

VREF

ICONST

CURRENT

VOLTAGE

CHANNEL1

CURRENT

VOLTAGE

CHANNEL2

CURRENT

VOLTAGE

CHANNEL3

4-1

MULTIPLEXER

VAUX0 (V)

VAUX1 (V)

VAUX2 (V)

VAUX3 (V)

MODECTRL REG <0..1>

COMP

ICONST

FILTER

V1L

V2L

V3L

VAUXL

PWMSYNC (CONVST)

MODECTRL

REG <07>

CLK

MODECTRL REG

<09..10..11>

ICONST_TRIM

REG <2:0>

CAPACITOR RESET

Figure 11. ADC Overview

Single Slope ADC Operations

The ADC conversion process is done by comparing each ADC

input to a reference ramp voltage and timing the comparison of

the two signals. The actual conversion point is the time-point

intersection of the input voltage and the ramp voltage (VC), as

shown in Figure 12. This time is converted to counts by the

12-bit ADC timer block and is stored in the ADC registers.

The ramp voltage used to perform the conversion is generated

by driving a fixed current into an off-chip capacitor, where the

capacitor voltage is:

VI C

C =×

()

Table V. Fundamental Characteristics of PWM Generation Unit of ADMC(F)341

Parameter

Min

Typ

Max

Unit

16-BIT PWM TIMER

Counter Resolution

Bits

Edge Resolution (Single Update Mode)

100

Edge Resolution (Double Update Mode)

Programmable Dead Time Range

102

µs

Programmable Dead Time Increments

100

Programmable Pulse Deletion Range

µs

Programmable Pulse Deletion Increments

PWM Frequency Range

153

78,431

PWMSYNC Pulsewidth (TCRST)

2.0

12.8

µs

Gate Drive Chop Frequency Range

0.02

MHz

NOTES

1153 Hz is calculated based on 16-bit resolution.

278,431 Hz is calculated based on 8-bit resolution.

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