MK2049-02/03

Communications Clock PLLs

MDS 2049-02/03 B

1

Revision 040601

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

• Packaged in 20 pin SOIC

• Fixed input-output phase relationship on most

clock selections

• Meets the TR62411, ETS300 011, and GR-1244

specification for MTIE, Pull-in/Hold-in Range,

Phase Transients, and Jitter Generation for

Stratum 3, 4, and 4E

• Accept multiple inputs: 8 kHz backplane clock,

Loop Timing frequencies, or 10-28 MHz

• Lock to 8 kHz ±100 ppm (External mode)

• Buffer Mode allows jitter attenuation of

10–28 MHz input and x1/x0.5 or x2/x4 outputs

• Exact internal ratios enable zero ppm error

• Output clock rates include T1, E1, T3, E3, ISDN,

xDSL, and OC3 submultiples

• 5 V ±5% operation. Refer to MK2049-34 for 3.3 V

The MK2049-02 and MK2049-03 are Phase-

Locked Loop (PLL) based clock synthesizers that

accept multiple input frequencies. With an 8 kHz

clock input as a reference, the MK2049-02/03

generate T1, E1, T3, E3, ISDN, xDSL, and other

communications frequencies. This allows for the

generation of clocks frequency-locked and phase-

locked to an 8 kHz backplane clock, simplifying

clock synchronization in communications systems.

The MK2049-02/03 can also accept a T1, E1, T3,

or E3 input clock and provide the same output for

loop timing. All outputs are frequency-locked

together and to the input.

These parts also have a jitter-attenuated buffer

capability. In this mode, the MK2049-02/03 are

ideal for filtering jitter from 27 MHz video clocks

or other clocks with high jitter.

ICS/MicroClock can customize these devices for

many other different frequencies. Contact your

ICS/MicroClock representative for more details.

Block Diagram

Description

Features

VDD

GND

PLL

Clock

Synthesis,

Control, and

Jitter

Attenuation

Circuitry

Output

Buffer

Output

Buffer

External/

Loop Timing

Mux

FS3:0

Clock

Input

CAP1

CAP2

CLK1

CLK2

Output

Buffer

CLK3

8 kHz

(External

Mode only)

Crystal

Oscillator

Reference

Crystal

X1

X2

4

4

3

RESET