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MK2049-02 Fiches technique(PDF) 3 Page - Integrated Circuit Systems

No de pièce MK2049-02
Description  Communications Clock PLLs
PDF  12 Pages
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Fabricant  ICST [Integrated Circuit Systems]
Site Internet  http://www.icst.com
Logo ICST - Integrated Circuit Systems

MK2049-02 Fiches technique(HTML) 3 Page - Integrated Circuit Systems

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MK2049-02/03
Communications Clock PLLs
MDS 2049-02/03 B
3
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
-0.5
VDD+0.5
V
Ambient Operating Temperature
MK2049-0xS
0
70
°C
MK2049-0xSI
-40
85
°C
Soldering Temperature
Max of 10 seconds
250
°C
Storage Temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5V unless noted)
DC CHARACTERISTICS (VDD = 5V unless noted)
Operating Voltage, VDD
4.75
5
5.25
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Input High Voltage, VIH
Pin 19 only
VDD-0.5
V
Input Low Voltage, VIL
Pin 19 only
0.5
V
Output High Voltage
IOH=-4 mA
VDD-0.4
V
Output High Voltage
IOH=-8 mA
2.4
V
Output Low Voltage
IOL=8 mA
0.4
V
Operating Supply Current, IDD
No Load, VDD=5.0V
20
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance, FS3:0
7
pF
AC CHARACTERISTICS (VDD = 5V unless noted)
AC CHARACTERISTICS (VDD = 5V unless noted)
Input Frequency, External Mode
ICLK
8.000
kHz
Input Clock Pulse Width
10
ns
Propagation Delay
ICLK to CLK2
0
2
ns
Output-Output Skew, Zero Delay Selections
CLK1 to CLK2, Note 2
500
ps
Output Clock Rise Time
0.8 to 2.0 V
1.5
ns
Output Clock Fall Time
2.0 to 0.8 V
1.5
ns
Output Clock Duty Cycle, High Time
At VDD/2
40
60
%
Actual mean frequency error versus target
Any clock selection
0
0
ppm
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CLK1 in the MK2049-02 may have the rising or falling edge aligned with the rising edge of CLK2. See the INPUT AND
OUTPUT SYNCHRONIZATION section for more details.
Electrical Specifications



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