MK2049-02/03

Communications Clock PLLs

MDS 2049-02/03 B

9

Revision 040601

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

External Components Selection

CAP2

CAP1

0.015 µF

470 k

Ω

0.1 µF

Crystal Operation

Figure 4. Loop Filter Component Values

Typical component values are shown. Contact the ICS MicroClock applications

department at (408)297-1201 for the recommended values for your application.

The MK2049 operates by phase locking the input signal to a VCXO which consists of the special

recommended crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best

performance and reliability, the layout guidelines shown on the previous page must be closely followed.

The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected

to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal.

External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To

achieve this, the layout should use short traces between the MK2049 and the crystal.

The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 4 below, and as

close to the chip as possible. High quality ceramic capacitors are recommended. DO NOT use any type of

polarized or electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another

alternative is the Panasonic PPS polymer dielectric series; their part number for the 0.1 µF cap is

ECHU1C104JB5. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have

piezolectric properties allow mechanical vibration in the system to increase the output jitter because the

mechanical energy is converted directly to voltage noise on the VCO input.

LAYOUT AND EXTERNAL COMPONENTS (continued)