MK2049-02/03

Communications Clock PLLs

MDS 2049-02/03 B

4

Revision 040601

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com

• 0 = connect directly to ground, 1 = connect directly to VDD.

• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.

MK2049-02 Output Decoding Table – External Mode (MHz)

ICLK

FS3 FS2 FS1 FS0

CLK1

CLK2

Crystal

CLK3

(Note 3)

8 kHz

0

0

0

0

1.544

3.088

12.352

8 kHz

8 kHz

0

0

0

1

2.048

4.096

12.288

8 kHz

8 kHz

0

0

1

0

22.368

44.736

11.184

8 kHz

8 kHz

0

0

1

1

17.184

34.368

11.456

8 kHz

8 kHz

0

1

0

0

19.44

38.88

12.96

8 kHz

8 kHz

0

1

0

1

16.384

32.768

8.192

8 kHz

8 kHz

0

1

1

0

24.576

49.152

12.288

8 kHz

8 kHz

0

1

1

1

25.92

51.84

12.96

8 kHz

8 kHz

1

1

0

0

10.24

20.48

10.24

8 kHz

8 kHz

1

1

0

1

4.096

8.192

12.288

8 kHz

ICLK

FS3 FS2 FS1 FS0

CLK1

CLK2

Crystal

CLK3

(Note 3)

1.544

1

0

0

0

1.544

3.088

12.352

N/A

2.048

1

0

0

1

2.048

4.096

12.288

N/A

44.736

1

0

1

0

22.368

44.736

11.184

N/A

34.368

1

0

1

1

17.184

34.368

11.456

N/A

MK2049-02 Output Decoding Table – Loop Timing Mode (MHz)

ICLK

FS3 FS2 FS1 FS0

CLK1

CLK2

Crystal

CLK3

(Note 3)

19 - 28

1

1

1

0

ICLK/2

ICLK

ICLK/2

N/A

10 - 14

1

1

1

1

2*ICLK

4*ICLK

ICLK

N/A

MK2049-02 Output Decoding Table – Buffer Mode (MHz)

Note 3: CLK1 rising or falling edge may align with the input clock. See Figure 1 on page 6

for more details.

= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.