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PSD833F2 Fiches technique(PDF) 90 Page - STMicroelectronics

No de pièce PSD833F2
Description  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD833F2 Fiches technique(HTML) 90 Page - STMicroelectronics

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Initial delivery state
PSD8XXFX
90/128
Doc ID 7833 Rev 7
20
Initial delivery state
When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The
PSD Configuration register bits are set to ’0.’ The code, configuration, and PLD logic are
loaded using the programming procedure. Information for programming the device is
available directly from ST. Please contact your local sales representative.
Table 36.
JTAG Enable register(1)
1.
The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are
dedicated by an NVM Configuration bit (via PSDsoft Express). However, Reset (RESET) prevents or
interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals.
Bit
Name
Description
Bit 0
JTAG_Enable
0 =
off
JTAG port is disabled.
1 =
on
JTAG port is enabled.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
X
0
Not used, and should be set to zero.
Bit 4
X
0
Not used, and should be set to zero.
Bit 5
X
0
Not used, and should be set to zero.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
Obsolete
Product(s)
- Obsolete
Product(s)



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