PSD833F2 datasheet(67/128 Pages) STMICROELECTRONICS

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PSD8XXFX

I/O ports

Doc ID 7833 Rev 7

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I/O ports

There are four programmable I/O ports: ports A, B, C, and D. Each of the ports is eight bits

except port D, which is 3 bits. Each port pin is individually user configurable, thus allowing

multiple functions per port. The ports are configured using PSDsoft Express Configuration

or by the MCU writing to on-chip registers in the CSIOP space.

The topics discussed in this section are:

●

General port architecture

●

Port operating modes

●

Port configuration registers (PCR)

●

Port Data registers

●

Individual port functionality.

16.1

General port architecture

The general architecture of the I/O port block is shown in Figure 25. Individual port

architectures are shown in Figure 27, Figure 28, Figure 29, and Figure 30. In general, once

the purpose for a port pin has been defined, that pin is no longer available for other

purposes. Exceptions are noted.

As shown in Figure 25, the ports contain an output multiplexer whose select signals are

driven by the configuration bits in the Control registers (Ports A and B only) and PSDsoft

Express Configuration.Inputs to the multiplexer include the following:

●

Output data from the Data Out register

●

Latched address outputs

●

CPLD macrocell output

●

External Chip Select (ECS0-ECS2) from the CPLD.

The port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be

read. The port Data Buffer (PDB) is connected to the Internal data bus for feedback and can

be read by the MCU. The Data Out and macrocell outputs, Direction and Control registers,

and port pin input are all connected to the port data buffer (PDB).

The port pin’s tri-state output driver enable is controlled by a two input OR gate whose

inputs come from the CPLD AND Array enable product term and the Direction register. If the

enable product term of any of the Array outputs are not defined and that port pin is not

defined as a CPLD output in the PSDabel file, then the Direction register has sole control of

the buffer that drives the port pin.

The contents of these registers can be altered by the MCU. The port Data Buffer (PDB)

feedback path allows the MCU to check the contents of the registers.

Ports A, B, and C have embedded input macrocells (IMC). The input macrocells (IMC) can

be configured as latches, registers, or direct inputs to the PLDs. The latches and registers

are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array.

The outputs from the input macrocells (IMC) drive the PLD input bus and can be read by the

MCU (see Figure 16: Input macrocell).

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