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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L9803 Fiches technique(PDF) 23 Page - STMicroelectronics |
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L9803 Fiches technique(HTML) 23 Page - STMicroelectronics |
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23 / 126 page  L9803 Clocks, Reset, Interrupts & Power saving modes 23/126 A flag in the watchdog status register indicates if the last reset is a watchdog reset or not, before clearing by a write of this register. 3.3.4 Register Description Watchdog Control Register (WDGCR) Register Address: 002Ah — Read/Write Reset Value: 0111 1111 (7Fh) b7 = WDGA: Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled. b6-0 =T6-T0: 7 bit timer (Msb to Lsb) These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 become cleared). Watchdog Status Register (WDGSR) Register Address: 002Bh — Read/Write Reset Value(*): 0000 0000 (00h) b7-1 = not used b0 = WDGF: Watchdog flag. Set by a Watchdog Reset, cleared by software (writing zero) or Power On / Low Voltage Reset. This flag is useful for distinguishing Power On / Low Voltage Reset and Watchdog Reset. (*): Except in the case of Watchdog Reset. 3.4 Miscellaneous Register (MISCR) The Miscellaneous register allows the user to select the Slow operating mode and to set the clock division prescaler factor. Bits 3, 4 determine the signal conditions which will trigger an interrupt request on I/O pins having interrupt capability. Register Address: 0020h — Read/Write 7 0 WDGA T6 T5 T4 T3 T2 T1 T0 7 0 - - --- - - WDGF |
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