L9803 datasheet(56/126 Pages) STMICROELECTRONICS

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On-Chip Peripherals

L9803

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Bit 1 = IEDG2 Input Edge 2.

This bit determines which type of level transition on the ICAP2 pin will trigger the capture

A falling edge triggers the capture.

A rising edge triggers the capture.

Bit 0 = EXEDG External Clock Edge.

This bit determines which type of level transition on the external clock pin EXCLK will trigger

the free running counter.

A falling edge triggers the free running counter.

A rising edge triggers the free running counter.

STATUS REGISTER (SR)

Timer1 Register Address: 0033h

Timer2 Register Address: 0043h

Read Only

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

Bit 7 = ICF1 Input Capture Flag 1.

No input capture (reset value)

An input capture has occurred. To clear this bit, first read the SR register, then read or

write the low byte of the ICR1 (ICLR1) register.

Bit 6 = OCF1 Output Compare Flag 1.

No match (reset value)

The content of the free running counter has matched the content of the OCR1

the OCR1 (OCLR1) register.

Bit 5 = TOF Timer Overflow.

No timer overflow (reset value)

The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read

the SR register, then read or write the low byte of the CR (CLR) register.

Note:

Reading or writing the ACLR register do not clear TOF.

Bit 4 = ICF2 Input Capture Flag 2.

No input capture (reset value)

ICF1

OCF1

TOF

ICF2

OCF2

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