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KC73125UBA Fiches technique(PDF) 2 Page - Samsung semiconductor |
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KC73125UBA Fiches technique(HTML) 2 Page - Samsung semiconductor |
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2 / 18 page ![]() 1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC73125UBA 2 BLOCK DIAGRAM PIN DESCRIPTION Figure 1. Block Diagram Table 1. Pin Description Pin Symbol Description Pin Symbol Description 1 Φ V4 Vertical CCD transfer clock 4 9 VDD Output stage drain bias 2 Φ V3 Vertical CCD transfer clock 3 10 GND Ground 3 Φ V2 Vertical CCD transfer clock 2 11 SUB Substrate bias 4 Φ V1 Vertical CCD transfer clock 1 12 VL Protection circuit bias 5 GND Ground 13 Φ RS Charge reset clock 6 VGG Output stage gate bias 14 NC No connection 7 VSS Output stage source bias 15 Φ H1 Horizontal CCD transfer clock 1 8 VOUT Signal output 16 Φ H2 Horizontal CCD transfer clock 2 8 VOUT 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 VSS VGG GND Φ V1 Φ V2 Φ V3 Φ V4 VDD VL GND NC Φ H1 Φ H2 Φ RS SUB Horizontal Shift Register CCD (Top View) |
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