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KC73125UBA Fiches technique(PDF) 4 Page - Samsung semiconductor |
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KC73125UBA Fiches technique(HTML) 4 Page - Samsung semiconductor |
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4 / 18 page ![]() 1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC73125UBA 4 DC CHARACTERISTICS CLOCK VOLTAGE CONDITIONS Table 3. DC Characteristics Item Symbol Min. Typ. Max. Unit Remark Output stage drain bias VDD 14.55 15.0 15.45 V Output stage gate voltage VGG 1.75 2.0 2.25 V Output stage source voltage VSS Ground through 680 Ω V ±5% Substrate voltage adjustment range VSUB 7.0 14.5 V Fluctuation voltage range after substrate voltage adjusted ∆V SUB -3 3 % Protection circuit bias voltage VL The lowest vertical clock level Output stage drain current IDD 2.5 mA Table 4. Clock Voltage Conditions Item Symbol Min. Typ. Max. Unit Remark Read-out clock voltage VVH1, VVH3 14.55 15.0 15.45 V High level Vertical transfer clock voltage VVM1 ~ VVM4 -0.2 0.0 0.2 V Middle VVL1 ~ VVL4 -9.5 -9.0 -8.5 V Low Horizontal transfer clock voltage VHH1, VHH2 4.75 5.0 5.25 V High VHL1, VHL2 -0.2 0.0 0.2 V Low Charge reset clock voltage VRSH 4.75 5.0 5.25 V High VRSL -0.2 0.0 0.2 V Low Substrate clock voltage VΦSUB 20 23.0 25 V Shutter |
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