Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

Preview PDF HTML

STA2500D Fiches technique(PDF) 45 Page - STMicroelectronics

No de pièce STA2500D
Description  Bluetooth??V2.1 EDR ("Lisbon") for automotive applications
PDF  57 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA2500D Fiches technique(HTML) 45 Page - STMicroelectronics

Back Button STA2500D Datasheet HTML 41Page - STMicroelectronics STA2500D Datasheet HTML 42Page - STMicroelectronics STA2500D Datasheet HTML 43Page - STMicroelectronics STA2500D Datasheet HTML 44Page - STMicroelectronics STA2500D Datasheet HTML 45Page - STMicroelectronics STA2500D Datasheet HTML 46Page - STMicroelectronics STA2500D Datasheet HTML 47Page - STMicroelectronics STA2500D Datasheet HTML 48Page - STMicroelectronics STA2500D Datasheet HTML 49Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 45 / 57 page
background image
STA2500D
Digital interfaces
Doc ID 16067 Rev 1
45/57
Figure 22.
PCM interface timing
Table 27.
PCM interface parameters
Symbol
Description
Min.
Typ.
Max.
Unit
PCM Interface
FPCM_CLK Frequency of PCM_CLK (Slave)
128(1)
2048
4000(2)
kHz
FPCM_SYNC Frequency of PCM_SYNC
-
8
-
kHz
Psync_delay Delay of the starting of the first slot
0
-
255
cycles
Ss
Slot start (programmable for every slot)
0
-
255
cycles
D
Data size
8
-
16
bits
N
Number of slots per frame
1
-
3
-
1.
Note that it is not possible to use 16 bits in Slave case if pcm_clk is 128kHz. This is the only exception.
2.
In Master case, the maximum of PCM_CLK is 2048 kHz.
Table 28.
PCM interface timing (at PCM_CLK = 2048 kHz)
Symbol
Description
Min.
Typ.
Max.
Unit
tWCH
High period of PCM_CLK
200
-
-
ns
tWCL
Low period of PCM_CLK
200
-
-
ns
tWSH
High period of PCM_SYNC
200
-
-
ns
tSSC
Setup time, PCM_SYNC high to PCM_CLK low
100
-
-
ns
tSDC
Setup time, PCM_A/B input valid to PCM_CLK low
100
-
-
ns
tHCD
Hold time, PCM_CLK low to PCM_A/B input valid
100
-
-
ns
tDCD
Delay time, PCM_CLK high to PCM_A/B output valid
-
-
150
ns
D02TL557
PCM_CLK
tWCL
PCM_SYNC
PCM_A/B in
PCM_B/A out
MSB
MSB-1
MSB-2
MSB-3
MSB-4
MSB
MSB-1
MSB-2
MSB-3
MSB-4
tSSC
tWCH
tWSH
tHCD
tSDC
tDCD



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57


Fiches technique Télécharger

Go To PDF Page


Lien URL



ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Lien vers la fiche technique    |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com