STA2500D datasheet(44/57 Pages) STMICROELECTRONICS

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Digital interfaces

STA2500D

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Doc ID 16067 Rev 1

In Slave mode, all possible PCM_SYNC lengths are supported (including “short frame” (= 1

PCM_CLK period) and “long frame” (> 1 PCM_CLK period)). In Master mode, the length is

configurable (1 (“short frame”), 8 or 16 (“long frame”) PCM_CLK periods).

The start of the PCM data is configurable. One possible configuration is e.g. for a short

frame, the falling edge of the PCM_SYNC indicating the start of the PCM word. Another

possible configuration is e.g. for a long frame, the rising edge of the PCM_SYNC indicating

the start of the PCM word.

TX data are by default generated on the positive edge of PCM_CLK and expected to be

latched by the external device on the negative edge while RX data are latched on the

negative edge of PCM_CLK. But the inverted clock mode is also supported, whereby the

generation of TX data is on the negative edge and the latching of TX and RX data is on the

positive edge.

One additional PCM_SYNC signal can be provided via the GPIOs. See section 7.5 for more

details.

Figure 19.

PCM (A-law, µ-law) standard mode

Figure 20.

Linear mode

Figure 21.

Multislot operation

The PCM implementation supports from 1 up to 3 slots per frame with the following

parameters:

D02TL558

PCM_CLK

PCM_SYNC

PCM_A

PCM_B

125µs

D02TL559

PCM_CLK

PCM_SYNC

PCM_A

PCM_B

125

μs

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