STA2500D datasheet(37/57 Pages) STMICROELECTRONICS

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STA2500D

General specification

Doc ID 16067 Rev 1

37/57

Figure 12.

Wakeup by host through UART with handshake

Host pulls BT_WAKEUP high to wake-up BT Controller. HW starts driving

CLK_REQ_OUT_1 high (after 2*LP_CLK).

Host starts 13 MHz clock and distribute it when stable. Delay between

CLQ_REQ_OUT_1 and usage of stable clock is programmable in between 3 and 39

ms.

When BT Controller starts with clock, it sets “flow on” by putting UART_RTS low. There

is a fixed SW latency. Host can send commands.

BT Controller sets HOST_WAKEUP high telling to the Host it has events to send to the

Host.

When the Host is ready for data transmission, it asserts UART_CTS low.

6.11

Patch RAM

The STA2500D includes a HW block that allows patching of the ROM code.

Additionally, a SW patch mechanism allows replacing complete SW functions without

changing the ROM image.

A part of the RAM memory is used for HW and SW patches.

6.12

Download of SW parameter file

To change the device configuration a set of customizable parameters have been defined

and put together in one file, the parameter file. This Parameter File is downloaded at start-

up into the STA2500D.

Examples of parameters are: radio configuration, PCM settings etc.

The same HCI command is used to download the file containing the patches (both those for

the SW and HW mechanism).

A more detailed description of the SW parameter file is available upon request.

REF_CLK _IN

CLK _REQ _O UT_1

BT_WAKEUP

UART_RTS

UART_CTS

UART_RTS

HOST_WAKEUP

UART_RTS

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