STA2500D datasheet(17/57 Pages) STMICROELECTRONICS

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STA2500D

Pinout

Doc ID 16067 Rev 1

17/57

4.3

I/O Supply

The device STA2500D has two different I/O supplies: BT_VIO_A and BT_VIO_B.

The two different pins may be potentially connected to separate dedicated voltage supplies

in order to harmonize the digital levels to the platform.

They are linked to different interfaces as described in Table 15.

Table 14.

Configuration programming

BT_CONFIG_1 BT_CONFIG_2 BT_CONFIG_3

Communication

Protocol

BT_CLK_REQ_OUT_1 BT_CLK_REQ_OUT_2

H4 UART

Active high

Depending on SW

config

H4 UART

Active low

Depending on SW

config

Reserved

Enhanced H4 SPI(1)

Active high

Active low

Reserved

In order to get other SPI modes, the Host must send a specific configuration at start-up in addition of these configuration

pins.

Table 15.

I/O supply split diagram

I/O supply

name

Voltage

range [V]

Function

Associated pins

BT_VIO_A

1.65 - 2.85

Configuration

BT_CONFIG_1, BT_CONFIG_2, BT_CONFIG_3

Control

BT_WAKEUP

BT_RESETN

BT_CLK_REQ_OUT_1, BT_CLK_REQ_OUT_2

GPIO (JTAG)

BT_GPIO_8 (JTAG_TCK), BT_GPIO_9 (JTAG_TDI),

BT_GPIO_10 (JTAG_TMS), BT_GPIO_11 (JTAG_TDO),

BT_GPIO_16 (JTAG_NTRST)

PCM

BT_PCM_A, BT_PCM_B, BT_PCM_SYNC, BT_PCM_CLK

Control

BT_REG_CTRL

UART (SPI)

BT_UART_RXD (SPI_DI), BT_UART_TXD (SPI_DO),

BT_UART_RTS (SPI_CSN), BT_UART_CTS (SPI_CLK),

BT_HOST_WAKEUP (SPI_INT)

Control (GPIO)

BT_CLK_REQ_IN_1 (GPIO_1), BT_CLK_REQ_IN_2 (GPIO_2)

GPIO

BT_GPIO_0

BT_VIO_B

1.17 - 2.85

Low - power clock

BT_LP_CLK

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