PCI1221 datasheet(14/123 Pages) TI

14 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

PCI interface control

TERMINAL

NAME

PIN NUMBER

I/O

TYPE

FUNCTION

NAME

PDV

GHK

TYPE

DEVSEL

197

I/O

PCI device select. The PCI1221 asserts DEVSEL to claim a PCI cycle as the target device. As a

PCI initiator on the bus, the PCI1221 monitors DEVSEL until a target responds. If no target

responds before timeout occurs, the PCI1221 terminates the cycle with an initiator abort.

FRAME

193

I/O

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that

a bus transaction is beginning, and data transfers continue while this signal is asserted. When

FRAME is deasserted, the PCI bus transaction is in the final data phase.

GNT

168

C13

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1221 access to the PCI bus

after the current data transaction has completed. GNT may or may not follow a PCI bus request,

depending on the PCI bus parking algorithm.

IDSEL

182

C10

Initialization device select. IDSEL selects the PCI1221 during configuration space accesses.

IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.

IRDY

195

I/O

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase

of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY

are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.

PERR

199

I/O

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does

not match PAR when PERR is enabled through bit 6 of the command register.

REQ

169

B13

PCI bus request. REQ is asserted by the PCI1221 to request access to the PCI bus as an initiator.

SERR

200

PCI system error. SERR is an output that is pulsed from the PCI1221 when enabled through the

command register indicating a system error has occurred. The PCI1221 need not be the target of

the PCI cycle to assert this signal. When SERR is enabled in the control register, this signal also

pulses, indicating that an address parity error has occurred on a CardBus interface.

STOP

198

I/O

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI

bus transaction. STOP is used for target disconnects and is commonly asserted by target devices

that do not support burst data transfers.

TRDY

196

I/O

PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase

of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY

are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

PCI1221 Fiches technique(PDF) 14 Page - Texas Instruments

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