PCI1221 datasheet(13/123 Pages) TI

13 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

PCI address and data

TERMINAL

NAME

PIN NUMBER

I/O

TYPE

FUNCTION

NAME

PDV

GHK

TYPE

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

170

171

173

174

176

177

165

179

183

184

185

186

188

189

190

191

204

205

206

208

172

A13

E12

B12

A12

B11

C11

E13

F11

E10

F10

C12

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary

interface. During the address phase of a primary bus PCI cycle, AD31-AD0 contain a 32-bit address or

other destination information. During the data phase, AD31-AD0 contain data.

C/BE3

C/BE2

C/BE1

C/BE0

162

192

203

A15

I/O

PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During

the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command. During the data

phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1

(AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PAR

202

I/O

PCI bus parity. In all PCI bus read and write cycles, the PCI1221 calculates even parity across the

AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1221 outputs this parity

indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the

initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR).

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