Moteur de recherche de fiches techniques de composants électroniques
  French  ▼
ALLDATASHEET.FR

X  

Preview PDF HTML

A14100A-RQ208C Fiches technique(PDF) 42 Page - Actel Corporation

No de pièce A14100A-RQ208C
Description  Accelerator Series FPGAs - ACT 3Family
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricant  ACTEL [Actel Corporation]
Site Internet  http://www.actel.com
Logo ACTEL - Actel Corporation

A14100A-RQ208C Fiches technique(HTML) 42 Page - Actel Corporation

Back Button A14100A-RQ208C Datasheet HTML 38Page - Actel Corporation A14100A-RQ208C Datasheet HTML 39Page - Actel Corporation A14100A-RQ208C Datasheet HTML 40Page - Actel Corporation A14100A-RQ208C Datasheet HTML 41Page - Actel Corporation A14100A-RQ208C Datasheet HTML 42Page - Actel Corporation A14100A-RQ208C Datasheet HTML 43Page - Actel Corporation A14100A-RQ208C Datasheet HTML 44Page - Actel Corporation A14100A-RQ208C Datasheet HTML 45Page - Actel Corporation A14100A-RQ208C Datasheet HTML 46Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 42 / 68 page
background image
1-216
A14100A, A14V100A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
I/O Module Input Propagation Delays
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
3.3V Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
tINY
Input Data Pad to Y
2.8
3.2
3.6
4.2
5.5
ns
tICKY
Input Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCKY
Output Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tICLRY
Input Asynchronous
Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCLRY
Output Asynchronous
Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
Predicted Input Routing Delays1
tIRD1
FO=1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tIRD2
FO=2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tIRD3
FO=3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tIRD4
FO=4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tIRD8
FO=8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
I/O Module Sequential Timing
tINH
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
0.0
0.0
0.0
0.0
ns
tINSU
Input F-F Data Setup
(w.r.t. IOCLK Pad)
1.2
1.4
1.5
1.8
1.8
ns
tIDEH
Input Data Enable Hold
(w.r.t. IOCLK Pad)
0.0
0.0
0.0
0.0
0.0
ns
tIDESU
Input Data Enable Setup
(w.r.t. IOCLK Pad)
5.8
6.5
7.5
8.6
8.6
ns
tOUTH
Output F-F Data Hold
(w.r.t. IOCLK Pad)
0.7
0.8
1.0
1.0
1.0
ns
tOUTSU
Output F-F Data Setup
(w.r.t. IOCLK Pad)
0.7
0.8
1.0
1.0
1.0
ns
tODEH
Output Data Enable Hold
(w.r.t. IOCLK Pad)
0.3
0.4
0.5
0.5
0.5
ns
tODESU
Output Data Enable Setup
(w.r.t. IOCLK Pad)
1.3
1.5
2.0
2.0
2.0
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


Fiches technique Télécharger

Go To PDF Page


Lien URL



ALLDATASHEET vous a-t-il été utile ?  [ DONATE ] 

À propos de Alldatasheet   |   Publicité   |   Contactez-nous   |   Politique de confidentialité   |   Lien vers la fiche technique    |   Echange de liens   |   Fabricants
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com