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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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A14100A-RQ208C Fiches technique(PDF) 19 Page - Actel Corporation |
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A14100A-RQ208C Fiches technique(HTML) 19 Page - Actel Corporation |
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19 / 68 page  1-193 Accelerator Series FPGAs – ACT ™ 3 Family ACT 3 Timing Model* *Values shown for A1425A-3. Output Delays Internal Delays Input Delays tINH = 0.0 ns tINSU = 1.8 ns I/O CLOCK I/O Module D Q tICKY = 4.7 ns FIOMAX = 250 MHz tINY = 2.8 ns tIRD2 = 1.2 ns Combinatorial Logic Module tPD = 2.0 ns Sequential Logic Module I/O Module tRD1 = 0.9 ns tDHS = 5.0 ns I/O Module ARRAY CLOCK FHMAX = 250 MHz Combin- atorial Logic included in tSUD D Q D Q tOUTH = 0.7 ns tOUTSU = 0.7 ns tDHS = 5.0 ns tENZHS = 4.0 ns tRD1 = 0.9 ns tCO = 2.0 ns tSUD = 0.5 ns tHD = 0.0 ns tRD4 = 1.7 ns tRD8 = 2.8 ns Predicted Routing Delays tHCKH = 3.0 ns tCKHS = 7.5 ns (pad-pad) |
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