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H8S2245 Fiches technique(PDF) 237 Page - Renesas Technology Corp

No de pièce H8S2245
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
PDF  818 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8S2245 Fiches technique(HTML) 237 Page - Renesas Technology Corp

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Section 7 Data Transfer Controller
Rev.3.00 Mar. 26, 2007 Page 195 of 772
REJ09B0355-0300
7.3.5
Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in
normal mode.
Table 7.5
Register Information in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
Transfer
SAR
DAR
Figure 7.6 Memory Mapping in Normal Mode



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