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H8S2245 Fiches technique(PDF) 568 Page - Renesas Technology Corp |
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H8S2245 Fiches technique(HTML) 568 Page - Renesas Technology Corp |
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568 / 818 page ![]() Section 15 RAM Rev.3.00 Mar. 26, 2007 Page 526 of 772 REJ09B0355-0300 15.1.1 Block Diagram Figure 15.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFDC00 H'FFDC02 H'FFDC04 H'FFFBFE H'FFDC01 H'FFDC03 H'FFDC05 H'FFFBFF Figure 15.1 Block Diagram of RAM (Example with H8S/2246 in Advanced Mode) 15.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 15.1 shows the register configuration. Table 15.1 Register Configuration Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address. |
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