LT6232 datasheet(19/30 Pages) AD

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LTC6228/LTC6229

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 2. 7pF Feedback Cancels Parasitic Pole

inverting input will cause the part to oscillate, due to the

pole formed at 45MHz. Adding a capacitor of 7pF across

the feedback resistor as shown in Figure 2 will eliminate

any ringing or oscillation. In general, if the resistive feed-

back network results in a pole whose frequency lies within

the closed loop bandwidth of the amplifier, a capacitor can

be added in parallel with the feedback resistor to introduce

a zero whose frequency is close to the frequency of the

pole, improving stability.

Power Dissipation

Care must be taken to ensure that the junction tempera-

ture of the die does not exceed 150°C.

The junction temperature, TJ, is calculated from the ambi-

ent temperature, TA, power dissipation, PD, and thermal

resistance, θJA:

TJ = TA + (PD • θJA).

The power dissipation in the IC is a function of the supply

voltage, output voltage and load resistance. For a given

supply voltage with output load connected to mid supply,

the worst-case power dissipation PD(MAX) occurs when

the supply current is maximum and the output voltage at

half of either supply voltage for a given load resistance.

PD(MAX) is approximately (since IS actually changes with

output load current) given by:

PD(MAX) = (2 • VS • IS(MAX)) + (VS/2)2/RL

Example: For an LTC6228 in a 6-lead DC package operat-

ing on ±5V supplies and driving a 500Ω load to ground,

the worst-case power dissipation is approximately given

by PD(MAX)/Amp = (10 • 19mA) + (5)2/500 = 240mW.

At the Absolute Maximum ambient operating temperature,

the junction temperature under these conditions will be:

TJ = TA + (PD • θJA) = 125 + 0.24 • 80 = 144.2°C

which is slightly less than the absolute maximum junction

temperature for the LTC6228/LTC6229.

Refer to the Pin Configuration section for thermal resis-

tances of various packages

Board Layout and Bypass Capacitors

High speed and RF board layout techniques should be

used due to the very high speeds of the signals involved.

For the LTC6228 SOIC-8 package option, the feedback

should be taken from the FB pin rather than from the

output pin, to reduce signal trace length.

For high speed designs, minimizing parasitic inductance

is important. The use of capacitors where the electrodes

are terminated on the long side instead of the short side

(for example the use of 0306 instead of 0603 compo-

nents) can help in this regard.

Shutdown

The LTC6228/LTC6229 have shutdown pins (SHDN),

which disable the amplifiers and reduce the quiescent

current per channel to approximately 500µA. The SHDN

pin needs to be driven at least 2.75V below V+ to disable

amplifier operation. For total supply voltages of 5V and or

less, the amplifier can be disabled at a pin voltage of V+ –

2.65V. During shutdown, the output transistors Q15 and

Q14 in Figure 1 are placed into a high impedance state. If

SHDN is left floating, the pin is internally biased to 1.2V

below the positive supply, and the amplifier remains on.

6228 F02

7pF

CPAR

VIN

VOUT

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