LT6232 datasheet(17/30 Pages) AD

17 / 30 page

LTC6228/LTC6229

Rev. B

For more information www.analog.com

Circuit Description

The LTC6228/LTC6229 have an input signal range that

extends from the negative power supply to 1.2V below

the positive power supply. Figure 1 depicts a simplified

schematic of the amplifier. The input stage consists of

PNP transistors Q1 and Q2. At the input stage, devices

Q18 and Q19 act to cancel the bias current of the input

pairwhenbiascancellationisenabled.Bootstraptransistor

Q13 and R5 match the collector and emitter voltages of

Q11 and Q12, thus enhancing gain by improving output

impedance. By making the collector current of Q13 twice

that of Q11 and Q12, the base currents of Q11 and Q12

do not contribute towards mismatch between the collec-

tor currents of Q9 and Q8. This improves DC accuracy. A

pair of complementary common emitter stages, Q15 and

Q14, enables the output to swing to either rail. The SHDN

Interface block translates the SHDN signal into 2 signals,

pwr_dn for powering down the device (by deactivating

current sources I1 - I4) and putting the output in a high

impedance state (by shorting the bases of Q15/Q14 to the

suppliesviaM2andM1),anddisable_bias,whichdisables

the input bias cancellation circuit, by shorting the base of

Q19 to V– through M3.

Input Bias Current

The LTC6228 family has an input bias current of approxi-

mately 16μA. For the LTC6228 and the LTC6229DD10,

the input bias current can be reduced to under 2.5μA at

room temperature when the SHDN pin voltage is taken to

within 350mV of the positive power supply. This capabil-

ity enables the input bias current cancellation circuitry,

allowing the amplifiers to be used in DC applications

involving source impedances.

When input bias current cancellation is enabled and the

input common mode voltage is within approximately

500mV of V–, the bias cancellation is no longer effec-

tive, because transistors Q18 and Q19 in Figure 1 enter

saturation. The input bias current can then exceed 50μA

or higher, which is more than the input bias current

APPLICATIONS INFORMATION

Figure 1. LTC6228 Simplified Schematic Diagram

SHDN

6228 F01

V+

V–

V+

V–

Q16

Q15

Q11

Q17

Q18

+IN

ESDD1

SHDN

INTERFACE

BLOCK

pwr_dn

disable_bias

pwr_dn

–IN

ESDD4

ESDD6

ESDD5

OUT

V+

V–

ESDD3

ESDD2

Q19

Q10

Q14

Q13

Q12

BUFFER

AND

OUTPUT BIAS

pwr_dn

disable_bias

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