ADIS16501SLASHPCBZ datasheet(21/45 Pages) AD

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Data Sheet

ADIS16501

THEORY OF OPERATION

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Rev. B | 21 of 45

Table 6. Generic SPI Main Pin Names and Functions (Continued)

Mnemonic

Function

SCLK

Serial clock

MOSI

Main output, subordinate input

MISO

Main input, subordinate output

IRQ

Interrupt request

Embedded processors typically configure their serial ports for com-

municating with SPI subordinate devices such as the ADIS16501

by using control registers on the processor itself. Table 7 lists the

SPI protocol settings for the ADIS16501.

Table 7. Generic Main Processor SPI Settings

Processor Setting

Description

Main

ADIS16501 operates as subordinate

SCLK ≤ 10 MHz1

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence, see Figure 40 for coding

16-Bit Mode

Shift register and data length

1 A burst mode read requires this value to be ≤1.1 MHz (see Table 2 for more

information).

DATA READY (DR)

The factory default configuration provides users with a DR signal on

the DR pin (see Table 5), which pulses when the output data reg-

isters are updating. Connect the DR pin to an input pin on the em-

bedded processor and configure this pin to trigger data collection

on the second edge of the pulse on the DR pin. The MSC_CTRL

Figure 35 shows a DR signal with Register MSC_CTRL, Bit 0 = 1,

meaning that data collection must start on the rising edges of the

DR pulses.

Figure 35. Data Ready when Register MSC_CTRL, Bit 0 = 1 (Default)

During the start-up and reset recovery processes, the DR signal

can exhibit some transient behavior before data production begins.

Figure 36 shows an example of the DR behavior during startup,

and Figure 37 and Figure 38 provide examples of the DR behavior

during recovery from reset commands.

Figure 36. Data Ready Response During Startup

Figure 37. Data Ready Response During Reset Recovery (Register

GLOB_CMD, Bit 7 = 1)

Figure 38. Data Ready Response During Reset (RST = 0) Recovery

READING SENSOR DATA

Reading a single register requires two 16-bit cycles on the SPI:

one to request the contents of a register and another to receive

those contents. The 16-bit command code (see Figure 40) for a

read request on the SPI has three parts: the read bit (R/W = 0),

either address of the register, [A6:A0], and eight don’t care bits,

[DC7:DC0]. Figure 39 shows an example that includes two register

reads in succession. This example starts with DIN = 0x0C00 to

request the contents of the Z_GYRO_LOW register and follows with

0x0E00 to request the contents of the Z_GYRO_OUT register. The

sequence in Figure 39 also shows full duplex mode of operation,

which means that the ADIS16501 can receive requests on DIN

while also transmitting data out on DOUT within the same 16-bit

SPI cycle.

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