| Moteur de recherche de fiches techniques de composants électroniques |
|
AM29BDS640G Fiches technique(PDF) 64 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AM29BDS640G Fiches technique(HTML) 64 Page - Advanced Micro Devices |
|
64 / 77 page ![]() 62 Am29BDS640G 25903C2 May 9, 2006 Data Sheet AC Characteristics Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. “In progress” and “complete” refer to status of program operation. 3. A21–A12 are don’t care during command sequence unlock cycles. 4. Addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 5. Either CS# or AVD# is required to go from low to high in between programming command sequences. 6. The Synchronous programming operation is independent of the Set Device Read Mode bit in the Burst Mode Configuration Register. 7. AVD# must toggle during command sequence unlock cycles. 8. tAH = 45 ns. 9. CLK must not have an active edge while WE# is at VIL. Figure 24. Alternate Synchronous Program Operation Timings OE# CE# Data Addresses AVD WE# CLK VCC 555h PD tAH tWC tWPH tWP PA tVCS tDH tCH In Progress tWHWH1 VA Complete VA Program Command Sequence (last two cycles) Read Status Data tDS tAVDP A0h tACS tCAS tAVHC tCSW2 tAS (Note 8) |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |