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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM29BDS640G Fiches technique(PDF) 56 Page - Advanced Micro Devices |
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AM29BDS640G Fiches technique(HTML) 56 Page - Advanced Micro Devices |
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56 / 77 page  54 Am29BDS640G 25903C2 May 9, 2006 Data Sheet AC Characteristics Figure 17. Reduced Wait-State Handshaking Burst Mode Read Starting at an Odd Address Notes: 1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active rising edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a CLK synchronous burst mode. Da Da + 1 Da + n OE# DQ15-DQ0 A21-A0 Aa AVD# RDY CLK CE# tCAS tAAS tAVC tAVD tAAH tOE tRACC tOEZ tCEZ tIACC tBDH 7 cycles for initial access shown. Hi-Z Hi-Z Hi-Z 12 3 4 5 7 8 tRDYS tBACC tACC 6 |
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